1. Field of the Invention
The present invention relates to a method for forming a gate oxide film of a semiconductor device, and more specifically, a method for forming a gate oxide film of a semiconductor device capable of reducing amounts of electrons and holes, which are trapped in the oxide film.
2. Discussion of Related Art
An electrically erasable programmable flash memory cell demands a high voltage at the time of programming or erasing operation. Repetition of the programming and erasing operations with the high voltage results in occurrence of traps of electrons and holes in the gate oxide film of the flash memory cell. In turn, the electrons and holes trapped in the gate oxide film shift the gate voltage, which is applied to the gate of the cell. For example, if the programming and erasing operations are repeated by 10,000 to 1,000,000 times, the accumulation of the trapped charges shift the threshold voltage of the cell.
The trap of charges in the oxide film can be reduced by using a nitride oxide film. Namely, the occurrence of the trap of the charges can be suppressed by forming a barrier layer, which is made by combination of an oxide and nitrogen in the direction of the silicon substrate by means of N2O or N2 treatment at the time of growing the oxide film.
However, in case of the flash cell, the current flow occurs at both ends of the gate. Therefore, although the trap of charges in the direction of the silicon is suppressed by the barrier formed by the oxide and the nitrogen, the trap of charges in the direction of the polysilicon cannot be suppressed since there is no barrier formed by the oxide and nitrogen. Namely, the trap of charges in the direction of the substrate is suppressed, but the trap of charges in the direction of the polysilicon is not suppressed.
Now, a conventional method of forming a gate oxide film will be described with reference to FIGS. 1A to 1C.
As shown in FIG. 1A, a well formation process and an ion implantation process for controlling a threshold voltage of a cell are carried out on the semiconductor substrate 10. Next, a gate oxide film 20 is formed by using an oxidation process, and then, a polysilicon film 30 is formed above the gate oxide film 20.
Referring to FIG. 1B, a nitride film 40 is formed above the polysilicon film 30.
FIG. 1C is a cross-sectional view illustrating a state that the gate oxide 20 and a device isolation film are formed by performing a patterning process, a self-aligned contact oxidation process, a High Density Plasma (HDP) oxide film burying process, and a nitride film removing process for forming a device isolation film.
As described above, in case of the conventional method, the current flow occurs at both ends of the gate. Therefore, although the trap of charges in the direction of the silicon is suppressed by the barrier formed by the oxide and the nitrogen, the trap of charges in the direction of the polysilicon cannot be suppressed since there is no barrier formed by the oxide and nitrogen. Namely, the trap of charges in the direction of the substrate is suppressed, but the trap of charges in the direction of the polysilicon is not suppressed.